Tungsten work function engineering for dual metal gate nano-CMOS

J. K. Efavi; T. Mollenhauer; T. Wahlbrink; H. D.B. Gottlob; M. C. Lemme; H. Kurz

doi:10.1007/s10854-005-2310-8

Tungsten work function engineering for dual metal gate nano-CMOS

J. K. Efavi, T. Mollenhauer, T. Wahlbrink, H. D.B. Gottlob, M. C. Lemme, H. Kurz

AMO GmbH

Research output: Contribution to journal › Article › peer-review

16 Citations (Scopus)

Abstract

A buffer layer technology for work function engineering of tungsten for dual metal gate Nano-CMOS is investigated. For the first time, tungsten is used as a p-type gate material using 1 nm of sputtered Aluminum Nitride (AlN_x) as a buffer layer on silicon dioxide (SiO₂) gate dielectric. A tungsten work function of 5.12 eV is realized using this technology in contrast to a mid-gap value of 4.6 eV without a buffer layer. Device characteristics of a p-MOSFET on silicon-on-insulator (SOI) substrate fabricated with this technology are presented.

Original language	English
Pages (from-to)	433-436
Number of pages	4
Journal	Journal of Materials Science: Materials in Electronics
Volume	16
Issue number	7
DOIs	https://doi.org/10.1007/s10854-005-2310-8
Publication status	Published - Jul 2005
Externally published	Yes

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title = "Tungsten work function engineering for dual metal gate nano-CMOS",

abstract = "A buffer layer technology for work function engineering of tungsten for dual metal gate Nano-CMOS is investigated. For the first time, tungsten is used as a p-type gate material using 1 nm of sputtered Aluminum Nitride (AlNx) as a buffer layer on silicon dioxide (SiO2) gate dielectric. A tungsten work function of 5.12 eV is realized using this technology in contrast to a mid-gap value of 4.6 eV without a buffer layer. Device characteristics of a p-MOSFET on silicon-on-insulator (SOI) substrate fabricated with this technology are presented.",

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AU - Efavi, J. K.

AU - Mollenhauer, T.

AU - Wahlbrink, T.

AU - Gottlob, H. D.B.

AU - Lemme, M. C.

AU - Kurz, H.

PY - 2005/7

Y1 - 2005/7

N2 - A buffer layer technology for work function engineering of tungsten for dual metal gate Nano-CMOS is investigated. For the first time, tungsten is used as a p-type gate material using 1 nm of sputtered Aluminum Nitride (AlNx) as a buffer layer on silicon dioxide (SiO2) gate dielectric. A tungsten work function of 5.12 eV is realized using this technology in contrast to a mid-gap value of 4.6 eV without a buffer layer. Device characteristics of a p-MOSFET on silicon-on-insulator (SOI) substrate fabricated with this technology are presented.

AB - A buffer layer technology for work function engineering of tungsten for dual metal gate Nano-CMOS is investigated. For the first time, tungsten is used as a p-type gate material using 1 nm of sputtered Aluminum Nitride (AlNx) as a buffer layer on silicon dioxide (SiO2) gate dielectric. A tungsten work function of 5.12 eV is realized using this technology in contrast to a mid-gap value of 4.6 eV without a buffer layer. Device characteristics of a p-MOSFET on silicon-on-insulator (SOI) substrate fabricated with this technology are presented.

UR - https://www.scopus.com/pages/publications/24944445857

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JO - Journal of Materials Science: Materials in Electronics

JF - Journal of Materials Science: Materials in Electronics

IS - 7

ER -

Tungsten work function engineering for dual metal gate nano-CMOS

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