Abstract
A buffer layer technology for work function engineering of tungsten for dual metal gate Nano-CMOS is investigated. For the first time, tungsten is used as a p-type gate material using 1 nm of sputtered Aluminum Nitride (AlNx) as a buffer layer on silicon dioxide (SiO2) gate dielectric. A tungsten work function of 5.12 eV is realized using this technology in contrast to a mid-gap value of 4.6 eV without a buffer layer. Device characteristics of a p-MOSFET on silicon-on-insulator (SOI) substrate fabricated with this technology are presented.
Original language | English |
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Pages (from-to) | 433-436 |
Number of pages | 4 |
Journal | Journal of Materials Science: Materials in Electronics |
Volume | 16 |
Issue number | 7 |
DOIs | |
Publication status | Published - Jul 2005 |
Externally published | Yes |