Tungsten work function engineering for dual metal gate nano-CMOS

J. K. Efavi, T. Mollenhauer, T. Wahlbrink, H. D.B. Gottlob, M. C. Lemme, H. Kurz

Research output: Contribution to journalArticlepeer-review

16 Citations (Scopus)

Abstract

A buffer layer technology for work function engineering of tungsten for dual metal gate Nano-CMOS is investigated. For the first time, tungsten is used as a p-type gate material using 1 nm of sputtered Aluminum Nitride (AlNx) as a buffer layer on silicon dioxide (SiO2) gate dielectric. A tungsten work function of 5.12 eV is realized using this technology in contrast to a mid-gap value of 4.6 eV without a buffer layer. Device characteristics of a p-MOSFET on silicon-on-insulator (SOI) substrate fabricated with this technology are presented.

Original languageEnglish
Pages (from-to)433-436
Number of pages4
JournalJournal of Materials Science: Materials in Electronics
Volume16
Issue number7
DOIs
Publication statusPublished - Jul 2005
Externally publishedYes

Fingerprint

Dive into the research topics of 'Tungsten work function engineering for dual metal gate nano-CMOS'. Together they form a unique fingerprint.

Cite this