Nanoscale TiN metal gate technology for CMOS integration

M. C. Lemme; J. K. Efavi; T. Mollenhauer; M. Schmidt; H. D.B. Gottlob; T. Wahlbrink; H. Kurz

doi:10.1016/j.mee.2006.01.161

Nanoscale TiN metal gate technology for CMOS integration

M. C. Lemme, J. K. Efavi, T. Mollenhauer, M. Schmidt, H. D.B. Gottlob, T. Wahlbrink, H. Kurz

AMO GmbH

Research output: Contribution to journal › Article › peer-review

35 Citations (Scopus)

Abstract

A TiN metal gate technology including essential nanostructuring process steps is investigated. Complex interdependencies of material deposition, nanolithography, nanoscale etching and post fabrication annealing are taken into account. First, a reactive sputter process has been optimized for plasma damage and stoichiometry. Then, a two step etch process that yields both anisotropy and selectivity has been identified. Finally, MOS-capacitors with TiN/SiO₂ gate stacks fabricated with this technology have been exposed to rapid thermal annealing steps. TiN/SiO₂ interfaces are chemically stable up to 800 °C and yield excellent CV and IV characteristics.

Original language	English
Pages (from-to)	1551-1554
Number of pages	4
Journal	Microelectronic Engineering
Volume	83
Issue number	4-9 SPEC. ISS.
DOIs	https://doi.org/10.1016/j.mee.2006.01.161
Publication status	Published - Apr 2006
Externally published	Yes

Keywords

Metal gate
Nanoelectronics
Nanostructuring
RIE etching
TiN

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10.1016/j.mee.2006.01.161

Cite this

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title = "Nanoscale TiN metal gate technology for CMOS integration",

abstract = "A TiN metal gate technology including essential nanostructuring process steps is investigated. Complex interdependencies of material deposition, nanolithography, nanoscale etching and post fabrication annealing are taken into account. First, a reactive sputter process has been optimized for plasma damage and stoichiometry. Then, a two step etch process that yields both anisotropy and selectivity has been identified. Finally, MOS-capacitors with TiN/SiO2 gate stacks fabricated with this technology have been exposed to rapid thermal annealing steps. TiN/SiO2 interfaces are chemically stable up to 800 °C and yield excellent CV and IV characteristics.",

keywords = "Metal gate, Nanoelectronics, Nanostructuring, RIE etching, TiN",

author = "Lemme, \{M. C.\} and Efavi, \{J. K.\} and T. Mollenhauer and M. Schmidt and Gottlob, \{H. D.B.\} and T. Wahlbrink and H. Kurz",

year = "2006",

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T1 - Nanoscale TiN metal gate technology for CMOS integration

AU - Lemme, M. C.

AU - Efavi, J. K.

AU - Mollenhauer, T.

AU - Schmidt, M.

AU - Gottlob, H. D.B.

AU - Wahlbrink, T.

AU - Kurz, H.

PY - 2006/4

Y1 - 2006/4

N2 - A TiN metal gate technology including essential nanostructuring process steps is investigated. Complex interdependencies of material deposition, nanolithography, nanoscale etching and post fabrication annealing are taken into account. First, a reactive sputter process has been optimized for plasma damage and stoichiometry. Then, a two step etch process that yields both anisotropy and selectivity has been identified. Finally, MOS-capacitors with TiN/SiO2 gate stacks fabricated with this technology have been exposed to rapid thermal annealing steps. TiN/SiO2 interfaces are chemically stable up to 800 °C and yield excellent CV and IV characteristics.

AB - A TiN metal gate technology including essential nanostructuring process steps is investigated. Complex interdependencies of material deposition, nanolithography, nanoscale etching and post fabrication annealing are taken into account. First, a reactive sputter process has been optimized for plasma damage and stoichiometry. Then, a two step etch process that yields both anisotropy and selectivity has been identified. Finally, MOS-capacitors with TiN/SiO2 gate stacks fabricated with this technology have been exposed to rapid thermal annealing steps. TiN/SiO2 interfaces are chemically stable up to 800 °C and yield excellent CV and IV characteristics.

KW - Metal gate

KW - Nanoelectronics

KW - Nanostructuring

KW - RIE etching

KW - TiN

UR - https://www.scopus.com/pages/publications/33646019270

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DO - 10.1016/j.mee.2006.01.161

M3 - Article

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VL - 83

SP - 1551

EP - 1554

JO - Microelectronic Engineering

JF - Microelectronic Engineering

IS - 4-9 SPEC. ISS.

ER -

Nanoscale TiN metal gate technology for CMOS integration

Abstract

Keywords

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